PLL based ULA

Logo

PLL based ULA

Uniform Linear Antenna Array Experiment based on Phase Locked Loops

PLL block diagram

This website links to the repositories needed to recreate the hardware and software used in the the paper.

The aim of this project is to create a test bed for understanding phased arrays.

The main hardware used is the LTC6946-4 PLL chip.

The main PCB is an array of 5 LTC6946 chips with a common 10MHz reference input. Each PLL is controlled by a dedicated microcontroller which communicated with a custom desktop application.

The repositories for each component are

For academic referencing please use

Uniform Linear Antenna Array Experiment based on Phase Locked Loops, Anil Chepala, Vincent Fusco, Umair Naeem and Adrian McKernan, 2022